This application is based on, and claims priority to, Japanese application number 2002-012062, filed on Jan. 21, 2002, in Japan, and which is incorporated herein by reference.
Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices and method for fabricating those devices. More particularly, the present invention relates to a semiconductor device that employs interconnections, wiring lines and electrodes formed by plating, and a method for fabricating the same. Conventionally, various methods for forming wiring lines and electrodes are used. Among these methods, a plating method is widely used as a useful method for forming thin films.
Japanese Unexamined Patent Publication No. 10-64953 discloses a method for fabricating a wiring line and electrode by means of plating. The method described in the above publication is now described with reference to FIG. 1. A pilot metal layer 2 is formed on an insulating substrate 1, and pillars are then formed by plate growth in such a way as to use a photoresist layer 3 as a mask. The mask 3 has a plurality of openings having different sizes. The pillars are formed in plating liquid, and different amounts of fresh plating liquid are supplied to different sizes of openings. In other words, plating or growth progresses at different rates in different sizes of openings in the mask 3. The difference in plating or growth rate forms a thin plating layer (pillar) 4c in an opening having a relative small size, and a thick plating layer 4d in an opening having a relative large size. Thus, an opening having a relatively large size is formed in a position on the mask 3 in which a relatively thick plating layer is to be formed, while an opening having a relatively small size is formed in a position in which a relatively thin plating layer is to be formed.
As described above, the rate of supply of plating liquid depends on the area of the opening, so that the thickness (height) of the growth of plating is proportional to the supply of plating liquid. When plating is simultaneously applied to opening having different areas, a relatively thin plating layer is formed in an opening of a relatively small area, while a relatively thick plating layer is formed in an opening of a relatively large area. Therefore, it is impossible to simultaneously form a relatively thick plating layer in an opening having a relatively small area and a relatively thin plating layer in an opening having a relatively large area. It is also impossible to simultaneously form plating layers having different thicknesses in openings having an identical area.
Therefore, only plating interconnections that depend on the respective opening sizes can be formed on the same layer. In order to obtain plating layers that have different sizes but have the same height, the plate growth must be separately carried out for each of the different opening sizes. When the electrodes are formed by plating, these electrodes are grown to respective thicknesses depending on the opening sizes. This may cause bonding failure.
Accordingly, it is an object of the present invention to provide a method for fabricating a semiconductor device capable of controlling the plate growth rate and a semiconductor device fabricated by the method.
Additional objects and advantages of the present invention will be set forth in part in the description which follows, and, in part, will be obvious from the description, or may be learned by practice of the invention.
The foregoing objects of the present invention are achieved by providing a method for fabricating a semiconductor device including the steps of:
(a) forming a mask on a predetermined layer, said mask having a first opening at a given side of the predetermined layer and a second opening that continues to and is smaller than the first opening; and
(b) forming a plating layer on the predetermined layer by using the mask.
The objects of the present invention are also achieved by a method for fabricating a semiconductor device including the steps of:
(a) forming a mask on a predetermined layer, said mask having an opening;
(b) forming an overhang that covers part of the opening; and
(c) forming plating layers on the predetermined layer by using the mask, a growth rate of one of the plating layers formed in said opening partially covered by said overhang being equal to that of another one of the plating layers formed in another opening.
The objects of the present invention are also achieved by a semiconductor device including plating layers formed on a predetermined layer, the plating layers having different widths, an identical height, and an identical hardness.
The objects of the present invention are also achieved by a semiconductor device including plating layers formed on a predetermined layer, one of the plating layers having a first portion that vertically extends with a constant width, and a second portion that continues to the first portion and is wider than the first portion.